The present invention relates generally to an improved thin film metal-oxide-semiconductor field effect transistor (MOSFET) structure, and in particular to an improved thin film MOSFET formed in a single grain of polysilicon, and to a process for its formation.
As circuit density continues to increase, there is a corresponding drive to produce ever smaller field effect transistors (FETs). Field effect transistors have typically been formed by providing active areas within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. A technique finding greater application in achieving reduced transistor size is to form FETs with thin films, commonly referred to as xe2x80x9cthin film transistorxe2x80x9d (TFT) technology.
In the fabrication of TFTs, a thin film of material (typically polysilicon) with a substantially constant thickness is provided on an insulating substrate instead of a semiconductor chip. Source and drain regions are formed by ion implantation or diffusion, and gate insulators and gates are also formed, thus providing a FET having active and channel regions formed entirely within a thin film as opposed to a bulk substrate. The use of insulating substrates such as silicon dioxide, glass, or quartz decreases the cost of the completed device while offering benefits such as reduced bulk capacitance and increased operating speed. Because of these and other advantages, TFTs are especially desirable for use in memory and logic applications, particularly SRAMs, and in liquid crystal displays.
It is desirable in TFTs to use a film that is as thin as possible so that the channel region provides maximized desired on/off characteristics for the transistors. This thinness adversely affects source/drain region conductance, however, because the diminished volume of material creates undesirable elevated Vcc source/drain resistance. Another disadvantage of TFTs is poor electrical performance because of defects in the polysilicon film such as grain boundaries. The effects of grain boundary defects, which include unwanted energy levels in the forbidden band, alteration of etching properties, and changes in electrical properties such as the value of the source/drain current and threshold voltage, are magnified in TFTs because of their small size.
Grain size and grain boundary consistency has a significant effect on the electrical current flow characteristics of thin films. Current resistance occurs as electrons cross grain boundaries, especially boundaries perpendicular to the direction of current flow. The larger and more numerous the grain boundaries, the higher the resistance. Typical TFTs have multiple grain boundaries within them because the channel length of the devices is much larger than the film thickness, which is usually approximately the same as the grain size.
There is needed, therefore, a thin film MOSFET with a minimum of grain boundaries, such that the MOSFET is typically formed in a single grain of polysilicon. A simple method of fabricating a thin film MOSFET with a minimum of grain boundaries is also needed.
The present invention provides a vertical thin film MOSFET having improved electrical functioning due to the formation of the transistor in a single grain of polysilicon. Also provided is a method for its formation, in which the transistor is formed from a thin film of polysilicon having large columnar grains. The large grain size and columnar grain orientation of the thin film are provided by recrystallizing a thin amorphous silicon film, or by specialized deposition of the thin film. Ion implantation and annealing are then performed to form source and drain regions in the thin film, which is patterned to form individual thin film transistors. Because of the large grain size and columnar orientation, the FETs have no grain boundaries within them, thereby maximizing conductance and threshold voltage reliability.
Additional advantages and features of the present invention will be apparent from the following detailed description and drawings which illustrate preferred embodiments of the invention.